Compaq iPAQ H3600 Hardware Design Specification - Version 0.2f
Copyright Notice
May 2000
The information in this publication is subject to change without notice.
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Overview
The iPAQ H3600 is a small form-factor, multimedia-centric PDA with versatile
expansion capabilities. It has a 4096-color reflective TFT LCD, stereo audio
output to 3.5mm phone jack and an expansion pack connector, a built-in mono
microphone and speaker, a high performance/low power SA-1110 (206 MHz) CPU, up
to 32 megabytes of SDRAM, up to 32 megabytes of flash ROM, touch panel input,
function/application buttons/switches, FIR/SIR, a RS-232C serial port, a USB
client port, a notification/battery charger LED, and an expansion pack interface
connector.
The iPAQ H3600 main unit consists of main board, switch board, color LCD and
touch panel module, and lithium battery pack.
Document Conventions
The names of signals that are active low will have a '#' suffix.
1. Main board
The main board of the iPAQ H3600 consists of the SA-1110 CPU, flash ROM,
SDRAM, serial port (RS-232C), USB client port, FIR, touch panel interface,
stereo audio codec, audio in/out circuit, microcontroller, and the expansion pack
interface and connector.
1.1. SA-1110 CPU
The SA-1110 was chosen for its low power, high performance and high
integration of peripherals. The SA-1110 has the following features:
normal (full-on) mode, idle (power-down) mode, sleep (power-down) mode
32-way set-associative caches
16 kilobyte instruction cache, 8 kilobyte write-back data cache
32-entry MMUs
read/write buffer
Additional features built into SA-1110 chipset
Memory controller supporting ROM, synchronous mask ROM (SMROM), flash,
DRAM, synchronous DRAM (SDRAM), SRAM, and SRAM-like variable latency I/O
LCD controller
1-, 2-, or 4-bit gray-scale levels, 8-, 12-, or 16-bit color levels
Serial communications module supporting
SDLC, 230-Kbps UART
Touch-screen, audio, telecom port
Infrared data (IrDA) serial port
115 Kbps, 4 Mbps
Six-channel DMA controller
Integrated two-slot PCMCIA controller
Twenty-eight general-purpose I/O ports
Real-time clock with interrupt capability
On-chip oscillators for clock sources
Interrupt controller
Power-management features
Normal (full-on) mode
Idle (power-down) mode
Sleep (power-down) mode
Four general-purpose interruptible timers
12-Mbps USB device controller
Synchronous serial port (UCB1100, UCB1200, SPI, TI, Wire)
256 mini-ball grid array (mBGA)
1.1.1. Clock generators
SA-1110 uses only two crystals, 32.768 KHz and 3.6864 MHz, to generate all
frequency needed.
Please check SA-1110
Developer's Manual section 8.3 and Appendix B and C on the requirements of
these two crystals. The frequency column using 3.579545 MHz crystal is for
reference only, the iPAQ H3600 does not use this crystal in its design.
The core frequency can be programmed to the values in table below.
CCF<4..0>
Core Clock Frequency w/3.6864 MHz X'tal
Core Clock Frequency w/3.579545 MHz X'tal
00000
59.0 MHz
57.3 MHz
00001
73.7 MHz
71.6 MHz
00010
88.5 MHz
85.9 MHz
00011
103.2 MHz
100.2 MHz
00100
118.0 MHz
114.5 MHz
00101
132.7 MHz
128.9 MHz
00110
147.5 MHz
143.2 MHz
00111
162.2 MHz
157.5 MHz
01000
176.2 MHz
171.8 MHz
01001
191.7 MHz
186.1 MHz
01010
206.4 MHz
200.5 MHz
01011
221.2 MHz
214.8 MHz
01100 - 11111
Not Supported
1.1.2. CPU power down by changing CPU clock generator value
When powered on, the SA-1110 initially runs at its lowest frequency.
Software has to set the CPU to speed by changing core clock configuration
field(CCF<4:0>) in the power manager phase-locked loop (PLL) configuration
register (PPCR). For more detail, please see Table 8-1 in SA-1110
Developer's Manual section 8.2.
Software can set the CCF<4:0> to a lower speed to power down
the CPU during operation. Note that there will be a 150 microseconds period
during which the CPU can not respond to external events and that the OS timer is
stopped during this period. The programmer must take these side effects into
account when software uses this technique to power down. For more details,
please see SA-1110
Developer's Manual section 8.2.1.
When switching CPU clock rates, the access time register programming
of external devices such as flash memory, SDRAM, and PCMCIA/CF must be adjusted
since access times of these external devices are all derived from the CPU
clock.
1.2. Memory Map
Address range
Function
Description
1
0h0000 0000 - 0h07FF FFFF
Static Bank Select 0 (128 MB)
iPAQ H3600 onboard flash (MCS0#)
2
0h0800 0000 - 0h0FFF FFFF
Static Bank Select 1 (128 MB)
Reserved (MCS1#)
3
0h1000 0000 - 0h17FF FFFF
Static Bank Select 2 (128 MB)
Expansion pack (MCS2#)
4
0h1800 0000 - 0h1FFF FFFF
Static Bank Select 3 (128 MB)
Expansion pack (MCS3#)
5
0h2000 0000 - 0h2FFF FFFF
PCMCIA Socket 0 Space (256 MB)
Expansion pack PCMCIA/CF slot 0 Interface
6
0h3000 0000 - 0h3FFF FFFF
PCMCIA Socket 1 Space (256 MB)
Expansion pack PCMCIA/CF slot 1 Interface
7
0h4000 0000 - 0h47FF FFFF
Static Bank Select 4 (128 MB)
Static Memory or Variable Latency I/O Interface, 256
MB(MCS4#, MCS5#)
(Expansion pack MCS4#)
8
0h4800 0000 - 0h4FFF FFFF
Static Bank Select 5 (128 MB)
Extended I/O and PPSH use (MCS5#)
9
0h5000 0000 - 0h7FFF FFFF
Reserved (768 MB)
10
0h8000 0000 - 0h8FFF FFFF
Peripheral Control Module Registers
(256 MB)
11
0h9000 0000 - 0h9FFF FFFF
System Control Module Registers
(256 MB)
12
0hA000 0000 - 0hAFFF FFFF
Memory and Expansion Registers
(256 MB)
13
0hB000 0000 - 0hBFFF FFFF
LCD and DMA Registers (256 MB)
14
0hC000 0000 - 0hC7FF FFFF
DRAM Bank 0 (128 MB)
512 MB. The iPAQ H3600 uses bank 0 only.
15
0hC800 0000 - 0hCFFF FFFF
DRAM Bank 1 (128 MB)
Reserved
16
0hD000 0000 - 0hD7FF FFFF
DRAM Bank 2 (128 MB)
Reserved
17
0hD800 0000 - 0hDFFF FFFF
DRAM Bank 3 (128 MB)
Reserved
18
0hE000 0000 - 0hE7FF FFFF
Zeros Bank (128 MB)
Cache flush replacement data.
Reads return zero, 128 MB
19
0hE800 0000 - 0hFFFF FFFF
Reserved (384 MB)
1.2.1. Internal I/O
The memory-mapped registers in address range 0h80000000 to 0hBFFFFFFF allow
software access for controlling flash memory, SDRAM, PCMCIA, serial ports, LCD
controller, general purpose I/O (GPIO) and power management registers.
There are three kinds of GPIOs used on this system. The first is the SA-1110
internal GPIO(GPIO-xx), the second is the SA-1110 extended GPIO(EGPIO-xx), the
third is the microcontroller, GPIO (Px-xx). The SA-1110 GPIOs (GPIO-xx,
EGPIO-xx) are described in this section. The microcontroller GPIO(Px-xx) is
described in the microcontroller
GPIO section.
Connected to the system power ON/OFF mechanical button. (The
bounce of this button is less than 50ms.)
H
H
GPIO-1
I(L)
UP_IRQ#
Signal from the microcontroller to interrupt the CPU. This
is one of CPU wakeup sources. The microcontroller uses this interface to
wake the CPU from sleep mode.
H
H
GPIO-2
O
LDD8
LCD DATA 8, connected to LCM data interface
L
GPIO-3
O
LDD9
LCD DATA 9, connected to LCM data interface
L
GPIO-4
O
LDD10
LCD DATA 10, connected to LCM data interface
L
GPIO-5
O
LDD11
LCD DATA 11, connected to LCM data interface
L
GPIO-6
O
LDD12
LCD DATA 12, connected to LCM data interface
L
GPIO-7
O
LDD13
LCD DATA 13, connected to LCM data interface
L
GPIO-8
O
LDD14
LCD DATA 14, connected to LCM data interface
L
GPIO-9
O
LDD15
LCD DATA 15, connected to LCM data interface
L
GPIO-10
I(L)
CARD_IND1#
PCMCIA/CF socket 1 card inserted detection. Low indicates
card present. May be programmed as an edge interrupt source to notify the
socket services driver of card insertion or removal.
L
L
GPIO-11
I(L)
CARD_IRQ1#
PCMCIA/CF slot 1 IRQ
L
L
GPIO-12
O
CLK_SET0
Clock select 0 for audio codec clock generator
L
L
GPIO-13
O
CLK_SET1
Clock select 1 for audio codec clock generator
L
L
GPIO-14
I/O
L3_SDA
L3 DATA, to/from UDA1341 control interface
L
L
GPIO-15
O
L3_MODE
L3 MODE, to UDA1341 control interface
L
L
GPIO-16
O
L3_SCLK
L3 SCLK, to UDA1341 control interface
L
L
GPIO-17
I(L)
CARD_IND0#
PCMCIA/CF socket 0 card inserted detection. Low indicates
card present. May be programmed as an edge interrupt source to notify the
socket services driver of card insertion or removal.
GPIO-18
I(L)
KEY_ACT#
Center button of joypad over speaker. (Hot key signal input from the docking cradle.?)
Enables power to all audio circuitry besides the audio
output amplifier.
L
L
EGPIO12
O(H)
QMUTE
Mutes the onboard audio codec.
H
L
EGPIO13
O
IR_FSEL
FIR mode selection: H=FIR, L=SIR
L
L
EGPIO14
O(H)
LCD_5V_ON
Enables 5V to the LCD module.
H
L
EGPIO15
O(H)
LVDD_ON
Enables 9V and -6.5V to the LCD module.
H
L
1.3. Flash memory
The iPAQ H3600 contains 2 flash memory chips onboard, configured as a 32bit
wide data bus.
1.3.1 Flash memory configurations supported
Chip Size
Bank Size
Total Size per bank
Chip per bank
4Mx16(64Mb)
16 MB
16 MB
2
8Mx16(128Mb)
32 MB
32 MB
2
1.3.2 Flash memory timing configurations
Flash memory supports 4-word burst mode reads. The following table shows the
fastest read/write access time for both 64Mb and 128Mb Intel Strata flash
memory.
Flash ROM
Single read access time
Paged Read access time
Single write access time
4Mx16(64Mb)
120nS
120ns-25ns-25ns-25ns
120ns
8Mx16(128Mb)
150ns
150ns-25ns-25ns-25ns
150ns
1.4. SDRAM
The iPAQ H3600 contains 2 SDRAM chips configured as a 32 bit wide memory bus.
The SA-1110 can support up to 256Mb SDRAM chips. The 64/128/256 Mb SDRAM pin
assignment must be compatible with the iPAQ H3600.
The SDRAM clock can be programmed to half or quarter of CPU
clock.
CPU Clock frequency
SDAM clock frequency
SDRAM Cycle time
133 MHz
66 MHz
15ns
206 MHz
103 MHz/51.5 MHz
9.7ns/19.4ns
The iPAQ H3600 uses 100 MHz SDRAM which the vendor has verified meets
the SA-1110 timing at a memory clock rate of 103 MHz.
1.5. Serial ports
The iPAQ H3600 provides three interfaces to communicate with external
devices: RS-232C, FIR/SIR, and USB (client). The FIR/SIR is compliant with IrDA 1.2 and
is built-in. The fourth serial port is used for CPU/microcontroller
interprocessor communication.
1.5.1. RS-232C
The RS232 interface signals includes RXD, TXD, RTS, CTS, DCD, DTR, DSR. The
RS-232 signals are routed through the cradle connector. The RS-232C interface
uses SA-1110 serial port 3.
The DCD signal of the RS-232C interface may be used to interrupt or wake the
SA-1110. The RS-232C transceiver power is controlled by RS232_ON. The DTR is
always active as long as the RS-232C transceiver is on, and cannot be controlled
by the CPU.
The RS-232C transceiver and cradle connector are on a separate physical
module: the switch board.
1.5.2. IrDA: FIR/SIR
The iPAQ H3600 supports FIR/SIR. The FIR/SIR uses SA-1110 serial port 2 for
transmit and receive. The FIR/SIR module can be powered down by setting IR_ON low.
The FIR/SIR module can be switched to SIR compatible mode by setting IR_FSEL low.
The iPAQ H3600 does not support the consumer IR standard.
The FIR/SIR transmission range is 30cm.
1.5.3. USB client
The iPAQ H3600 is a USB peripheral at 12 Mbps.
This USB client uses SA-1110 serial port channel 0. The USB port is provided on
the cradle connector.
1.5.4. SA-1110/microcontroller inter-processor communication
serial interface
Serial port 1 of the SA-1110 is used for SA-1110 / microcontroller
inter-processor communication. This interface is LVTTL level with TXD and RXD
only. There are also two interprocessor interrupts: one for SA-1110 to interrupt
the microcontroller (CPU_IRQ#), and one for the microcontroller to interrupt the
SA-1110 (UP_IRQ#).
1.6. Audio system
The iPAQ H3600 onboard audio system communicates to a Philips UDA1341 code
through SA-1110 serial port 4 (MCP/SSP). The port is programmed in I2S and L3
mode. Digital audio sample rates (8 KHz, 11.025 KHz, 22.05 KHz, 44.1 Khz) are
generated by a hardware
clock generator.
Audio input is from the built-in microphone only.
Onboard audio output can be either the mono speaker or the stereo headphone
jack, and stereo line-out to the expansion pack. The headphone jack is 3.5mm
diameter and supports 3-wire stereo headphones. When a headphone is plugged in,
the internal mono speaker will be disabled automatically.
Because the SA-1110 serial codec interface is not routed to the expansion pack
connector, any audio codec in an expansion pack must support a parallel memory bus
interface.
1.6.1. Stereo codec
The UDA1341 audio codec can support 16, 18, or 20-bit digital audio data.
The power to each function block of UDA1341 can be controlled by issuing
power down commands to the UDA1341's power control registers.
1.6.2. Microphone
The iPAQ H3600 has a built-in microphone. The microphone signal is fed to
both the right and left audio channels.
1.6.3. Line in
There is no audio line in supported on the iPAQ H3600.
1.6.4. Speaker
The iPAQ H3600 has a built-in mono speaker. The speaker output is the sum of
right and left audio output channels. When a headphone/earphone is plugged into
the line out phone jack, the internal speaker will be automatically
disabled.
1.6.5. Line out
The iPAQ H3600 has two stereo outputs. The first uses the 3.5mm
diameter stereo phone jack; the second line out is to the expansion pack
connector.
1.6.5.1. Stereo Phone jack
The iPAQ H3600 stereo output is connected to the 3.5mm stereo phone jack
and is designed to drive a 32 ohm load. When a stereo headphone / earphone
is plugged into the line out phone jack it will automatically disable the
internal speaker. Mono headphone / earphone is not supported.
1.6.5.2. Expansion pack connector audio out
There is a stereo audio line-out to the expansion pack connector. This
line-out is buffered version of the audio codec output but is not capable of
driving a speaker. It is designed to drive a 20 Kohm load. This stereo output
is turned on whenever the audio codec is turned on.
The sampling rate clock generator of the iPAQ H3600 can generate 8 KHz,
11.025 KHz, 16 KHz, 22.05 KHz, 32 KHz, 44.1 KHz, and 48 Khz sampling rate
directly by a programmable clock generator. These sampling rates can be
generated according the following table. For 22.05 KHz, there are two
possibilities and the programmer is free to use either one.
Sampling rate
Codec Fs
Required Frequency
Clock gen. select CLK_SET(1..0)
Actual Frequency
Error(%)
8 KHz
512Fs
4.096 MHz
10
4.096 MHz
0
11.025 KHz
512Fs
5.6448 MHz
11
5.6245 MHz
-0.04
16 KHz
256Fs
4.096 MHz
10
4.096 MHz
0
22.05 KHz
256Fs
/512Fs
5.6448 MHz
/11.2896 MHz
11
/01
5.6245 MHz
11.2896 MHz
-0.04
/0
32 KHz
384Fs
12.288 MHz
00
12.288 MHz
0
44.1 KHz
256Fs
11.2896 MHz
01
11.2896 MHz
0
48 KHz
256Fs
12.288 MHz
00
12.288 MHz
0
1.6.7. External audio codec supported on expansion pack
If the iPAQ H3600 wants to support an external audio codec on an expansion pack,
the audio codec must support a parallel interface. The SA-1110 serial codec
interface is not connected to expansion pack. We recommend using the expansion pack
fast I/O mode. The fast I/O mode supports 32-bit burst access cycles.
1.7. Visual indication: LED
There are two LEDs for visual indications. One is AMBER to indicate main
battery charging (LED_ON#). The other is GREEN for user notification (CH_LED#).
These two LEDs are contained in the same package. When these two LEDs are turned
on at the same time, the color shown will be different from either one
individually. Software should ensure that only one of the LED's is enabled at
the same time to prevent confusion.
A microcontroller interfaces to the touch panel, battery charger,
key switch and other miscellaneous controls.
The communications protocol between the SA-1110 and the microcontroller is
described in TBD.
GPIO
I/O (Active)
Pin Name
Descriptions
Idle State
Hibernate State
PA0
O
M_ISET0
Battery charge current setting 0
PA1
I(=,A)
TEMP_BAT
Battery temperature sensor input
PA2
I(=,A)
LIT_SEN
Light sensor signal input
PA3
I(=,A)
IMIN
Charger current monitor
PA4
I(=,A)
VS_MBAT
Main battery 2/3 voltage sense input
PA5
I
KEY_IN
Key signal input. The keys connect this input to a voltage
divider.
PA6
I
TP_X1
Touch panel X-coordinate signal input
PA7
I
TP_Y1
Touch panel Y-coordinate signal input
PB0
I(L)
AC_IN#
AC adapter in indication. When AC adapter is inserted, this
signal will change the state to low and the WAKE_UP_EVENT# (PD2) is also
changed to low. PD2 will cause the microcontroller interrupt to wakeup
when the microcontroller is at sleep mode and do the charging service.
Then microcontroller changes the state of DIS_AC_IN (PC4) to high to
release the interrupt source. And the microcontroller will monitor the
state of PB0, if the state is changed to high that the AC adapter is
removed and change the state of DIS_AC_IN (PC4) to low.
PB1
O
CH_TIMER
Charger timing control
PB2
I(L)
KEY_PRESS#
Key pressed indication. When any key is pressed, this signal
is changed to low and the WAKE_UP_EVENT# (PD2) is also changed to low. PD2
will cause the microcontroller interrupt to wakeup when microcontroller is
at sleep mode and do KEY service. Then the microcontroller changes the
state of DIS_KEY_PRESS (PD6) to high to release the interrupt source. The
microcontroller will monitor the state of PB2, if the state is changed to
high when the KEY is not pressed and changes the state of DIS_KEY_PRESS
(PD6) to low.
PB3
I(L)
CPU_IRQ#
CPU to microcontroller interrupt signal. When the CPU is
wakeup from the sleep mode, this signal will change the state to low and
the WAKE_UP_EVENT# (PD2) is also changed to low. PD2 will cause the
microcontroller interrupt to wakeup when the microcontroller is at sleep
mode. Then microcontroller changes the state of DIS_CPU_IRQ (PD7) to high
to release the interrupt source. The microcontroller will monitor the
state of PB3, if the state is changed to high that the CPU is went to
sleep mode and change the state of DIS_CPU_IRQ (PD7) to low
PB4
O(L)
LED_ON#
Notification LED ON
H
H
PB5
O
SPI_DO
SPI interface data out
H
H
PB6
I
SPI_CLK
SPI interface clock
PB7
I
SPI_DI
SPI interface data in
L
L
PC0
O(H)
IN_Y0
Touch panel control signal Y0. When the touch panel is
pressed i.e. PEN_IRQ# (PD3) will cause the microcontroller interrupt to
perform touch panel service. Change PC0 to high and PC1 to low to sense
the Y-coordinate.
L
L
PC1
O(L)
IN_Y1#
Touch panel control signal Y1. When the touch panel is
pressed i.e. PEN_IRQ# (PD3) will cause the microcontroller interrupt to
perform touch panel service. Change PC0 to high and PC1 to low to sense
the Y-coordinate.
H
H
PC2
O(L)
IN_X1#
Touch panel control signal X1. When the touch panel is
pressed i.e. PEN_IRQ# (PD3) will cause the microcontroller interrupt to
perform touch panel service. Change PC2 to low and PC3 to high to sense
the X-coordinate.
H
H
PC3
O(H)
IN_X0
Touch panel control signal X0. When the touch panel is
pressed i.e. PEN_IRQ# (PD3) will cause the microcontroller interrupt to
perform touch panel service. Change PC2 to low and PC3 to high to sense
the X-coordinate.
L
L
PC4
O(H)
DIS_AC_IN
Disable AC_IN# interrupt request. When AC adapter is
inserted and generated a interrupt signal WAKE_UP_EVENT# (PD2) to the
microcontroller and perform the charging service. Then the microcontroller
changes the state of DIS_AC_IN to high to release the interrupt source.
The microcontroller will monitor the state of PB0, and if the state is
changed to high, that the AC adapter is removed, it will change the state
of DIS_AC_IN to low.
L
PC5
O(L)
UP_IRQ#
Microcontroller to CPU interrupt. When the microcontroller
has a request to the CPU, it can use this GPIO to interrupt the CPU.
H
PC6
I(L)
CH_LED#
Charger LED on
PC7
I(H)
FL_PWR_ON
Front light power on
L
PD0
I
UP_TXD
CPU-microcontroller inter comm. serial port
PD1
O
UP_RXD
CPU-microcontroller inter comm. serial port
PD2
I(L)
WAKE_UP_EVENT#
Wake up event from key input. This is a interrupt pin and
there are three interrupt sources, AC adapter inserted indication to do
the charging service; KEY pressed indication to do the KEY service; CPU
waked up from the sleep mode to indicate the microcontroller.
PD3
I(L)
PEN_IRQ#
Touch panel interrupt. When touch panel is pressed that this
GPIO will cause the microcontroller interrupt to do touch panel
service.
PD4
O
PWM_OUT
PWM for CCFL brightness control
L
L
PD5
O(L)
SPI_CS#
SPI chip select
PD6
O(H)
DIS_KEY_PRESS
Disable key press. When any key is pressed and generated a
interrupt signal WAKE_UP_EVENT# (PD2) to microcontroller and perform KEY
service. Then the microcontroller changes the state of DIS_KEY_PRESS to
high to release the interrupt source. The microcontroller will monitor the
state of PB2, if the state is changed to high when the KEY is not pressed
and change the state of DIS_KEY_PRESS to low.
L
L
PD7
O(H)
DIS_CPU_IRQ
Disable CPU interrupt. When the CPU is waked up from the
sleep mode and generated an interrupt signal WAKE_UP_EVENT# (PD2) to
indicate the microncontroller. Then the microcontroller changes the state
of DIS_CPU_IRQ to high to release the interrupt source. The
microcontroller will monitor the state of PB3, if the state is changed to
high that the CPU is went to sleep mode and change the state of
DIS_CPU_IRQ to low.
L
L
1.9. Touch panel interface
The touch panel is controlled by the following procedure, executed by the
microcontroller.
Step
Control
Action
0
IN_Y1#=1, IN_Y0=0, IN_X1#=1, IN_X0=0.
Turn off touch panel interface to power down
1
IN_Y1#=1, IN_Y0=0, IN_X1#=1, IN_X0=0.
Waiting for touch panel interrupt PEN_IRQ#. If interrupt
occurred, then go to step 2.
2
IN_Y1#=1, IN_Y0=0, IN_X1#=0, IN_X0=1.
Sense X coordinate TP_X0, go to step 3
3
IN_Y1#=0, IN_Y0=1, IN_X1#=1, IN_X0=0.
Sense Y coordinate TP_Y1, go to step 0 or 1, depends on
software implementation.
The touch panel
connector is defined as following.
Pin number
Pin Name
Function
1
NC
2
Y1
Y terminal positive end
3
NC
4
X0
X terminal negative end
5
NC
6
Y0
Y terminal negative end
7
NC
8
X1
X terminal positive end
9
NC
Please note that the pitch and pin number of touch panel connector
on main board is different from the connector of LCD flex cable, but are
compatible.
1.10. Key/buttons
The iPAQ H3600 main unit has a 5-button joystick, 4 application buttons, one
recording button, on power/CCFL on/off switch, one reset button and one main
battery on/off switch..
1.10.1. Sense voltage level for switches and buttons
Some of the switches or buttons are daisy chained into a resistor network.
The pressing of switch or button are sensed by the voltage level of resistor
network. The voltage step of the ADC is 0.0029V(3.0V/1024).
Switch No.
Name
Voltage level(V)
1
RECORD_SW
0
2
AP1_SW
0.598
3
AP2_SW
0.890
4
AP3_SW
1.167
5
AP4_SW
1.452
6
KEY_UP
1.734
7
KEY_RIGHT
2.017
8
KEY_LEFT
2.296
9
KEY_DOWN
2.579
1.11. Internal LCDC and LCD interface connector
The iPAQ H3600 internal LCDC uses DMA from main memory.
The screen refresh bandwidth required for 320x240 with 70Hz refresh rate
16bit color LCD display is
(320 x 240 x 16 / 8) x 70=153600 x 70 = 10752000 byte/sec = 10.752
Mbyte/sec
The LCD controller is programmed in 16-bit TFT mode, but the TFT LCD uses the
most highest 4 bit for each color(RGB). That makes a total of 4096 colors.
Unused bits are discarded and cannot be redefined as GPIO.
The outputs of internal LCDC are fed to LCD timing controller to translate to
proper timing and wave form for LCD module. There is a reference voltage driver
for setting the LCD's gamma.
1.11.1. LCD timing controller
In order to translate the LCDC outputs to be acceptable by SONY 4096-color
TFT, we use a LCD timing controller SONY CXD3508TQ.
1.11.2. LCD gamma reference voltage driver
A reference voltage driver will generate a set of voltages for LCD gamma
reference. The required voltages are listed in following table.
The PCMCIA/Memory/fast I/O interfaces shared the same connector pins. These
pins function differently cycle by cycle depends on which memory space, i.e.
PCMCIA, Memory, fast I/O is accessed.
1.12.1. Pin definitions
Signal types are referenced to the expansion pack. For example, signal type
'I' indicates from CPU to Expansion pack. Type 'O' means from Expansion
pack to CPU.
Pin #
Name
Type
Descriptions
Pin #
Name
Type
Descriptions
1
CC-ETM
O
Charge current pin
51
ODET1#
O
Expansion pack detect
2
PCM_RESET
I
PCMCIA Reset
52
Reserved
3
VS_EBAT
O
Extended battery sense
53
DQM3
I
Memory & I/O byte enable
4
RD/WR#
I
Memory & I/O Read/Write#
54
DQM0
I
Memory & I/O byte enable
5
GND
55
VDD
6
RDY
O
I/O ready signal
56
DQM1
I
Memory & I/O byte enable
7
CEN_ETM
I/O
Charger current enable
57
BATT_FLT
O
Extended battery fault
8
RESET
I
GP reset for expansion pack
58
PCM_IRQ#1
O
PCMCIA 1st socket RDY/IRQ#
9
INT_OP
I
Expansion Pack Interrupt
59
PCM_CE1#
I
PCMCIA card enable
10
CD_SCKT1#
O
PCMCIA 1st socket detect
60
PCM_OE#
I
CF Output enable pin
11
PSKTSEL
I
PCMCIA socket select
61
PCM_WE#
I
PCMCIA write enable
12
PCM_CE2#
I
PCMCIA card enable
62
CD_SCKT2#
O
PCMCIA 2nd socket detect
13
PCM_IORD#
I
PCMCIA IO Read
63
PCM_IRQ#2
O
PCMCIA 2nd socket RDY/IRQ#
14
PCM_IOWR#
I
PCMCIAF IO Write
64
D03
I/O
PCMCIA/Memory Data
15
D11
I/O
PCMCIA/Memory Data
65
D04
I/O
PCMCIA/Memory Data
16
D12
I/O
PCMCIA/Memory Data
66
GND
17
D13
I/O
PCMCIA/Memory Data
67
D05
I/O
PCMCIA/Memory Data
18
D14
I/O
PCMCIA/Memory Data
68
D06
I/O
PCMCIA/Memory Data
19
D15
I/O
PCMCIA/Memory Data
69
D07
I/O
PCMCIA/Memory Data
20
A17/D22
I/O
PCMCIA/Memory Addr/Data
70
A10
I
PCMCIA/Memory Address
21
GND
71
A11/D16
I/O
PCMCIA/Memory Addr/Data
22
A18/D23
I/O
PCMCIA/Memory Addr/Data
72
A09
I
PCMCIA/Memory Address
23
A19/D24
I/O
PCMCIA/Memory Addr/Data
73
A08
I
PCMCIA/Memory Address
24
A20/D25
I/O
PCMCIA/Memory Addr/Data
74
A13/D18
I/O
PCMCIA/Memory Addr/Data
25
A21/D26
I/O
PCMCIA/Memory Addr/Data
75
A14/D19
I/O
PCMCIA/Memory Addr/Data
26
A22/D27
I/O
PCMCIA/Memory Addr/Data
76
GND
27
A23/D28
I/O
PCMCIA/Memory Addr/Data
77
A16/D21
I/O
PCMCIA/Memory Addr/Data
28
A24/D29
I/O
PCMCIA/Memory Addr/Data
78
A15/D20
I/O
PCMCIA/Memory Addr/Data
29
A25/D30
I/O
PCMCIA/Memory Addr/Data
79
A12/D17
I/O
PCMCIA/Memory Addr/Data
30
D08
I/O
PCMCIA/Memory Data
80
A07
I
PCMCIA/Memory Address
31
GND
81
A06
I
PCMCIA/Memory Address
32
D09
I/O
PCMCIA/Memory Data
82
A05
I
PCMCIA/Memory Address
33
D10
I/O
PCMCIA/Memory Data
83
A04
I
PCMCIA/Memory Address
34
D00
I/O
PCMCIA/Memory Data
84
A03
I
PCMCIA/Memory Address
35
D01
I/O
PCMCIA/Memory Data
85
A02
I
PCMCIA/Memory Address
36
D02
I/O
PCMCIA/Memory Data
86
GND
37
D31
I/O
PCMCIA/Memory Data
87
A01
I
PCMCIA/Memory Address
38
PCM_REG#
I
PCMCIA IO cycle
88
A00
I
PCMCIA/Memory Address
39
PCM_WAIT#
O
PCMCIA Wait
89
PCM_WP
O
PCMCIA WP/IOIS16#
40
SPI_DI
I
SPI Data In to expansion pack
90
A_OUTR
I
Right audio channel
41
SPI_CS#
I
SPI chip select
91
A_OUTL
I
Left audio channel
42
MCS2#
I
Memory Chip Select
92
A_GND
Analog GND for audio
43
MWE#
I
Memory Write Enable
93
Reserved
44
MOE#
I
Memory Output Enable
94
MCS4#
I
Memory Chip Select
45
GND
95
VDD
46
EBAT_ON
O
Extended battery power OK
96
SPI_SCK
I
SPI Clock Signal
47
OPT_ON
I
Expansion pack enable
97
MCHG_EN
I
Main battery recharging
48
V_ADP
I/O
Positive of AC adapter
98
V_ADP
I/O
Positive of AC adapter
49
V_EBAT
O
Positive of expansion battery
99
V_EBAT
O
Positive of expansion battery
50
ODET2#
O
Expansion pack detect
100
SPI_DO
O
SPI Data Out from expansion pack
Notes: 1) Signal type referenced to the expansion
pack. 2) All power and ground pins protrude from the other pins for hot
plugging.
Detailed Pin Description:
PCMCIA/Compact Flash/Memory/Fast I/O
Signal Name
Dir.
Description
A10 - A00
I
PCMCIA/CF/Memory address pins used to address card or expansion
pack in Memory, I/O or True IDE
A25 - A11
PCMCIA or memory address pins used to access devices in the
expansion pack. These pins are shared with D31:D16.
D15 - D00
I/O
Data pins used for 16-bit accesses in standard CF/PCMCIA, memory or I/O modes
D31 - D16
Data pins for special accesses, 32-bit read and write accesses in PCMCIA, CF, I/O or
memory modes. These pins are shared with A25:A11.
PCM_CE1#, PCM_CE2#
I
PCMCIA/CF card enable for 8 or 16-bit select in memory and I/O mode. Functions as
CS0# and CS1# in IDE mode.
CD_SCKT1#, CD_SCKT2#
O
PCMCIA/CF card detect pins for devices 1 and 2. CD_SCKT1# represents logical OR of
CD1# and CD2# fo PCMCIA/CF pins.
PCM_IORD#
I
PCMCIA/CF pin used in I/O and IDE modes as read strobe
PCM_IOWR#
I
PCMCIA/CF pin used in I/O and IDE modes as read strobe
PCM_OE#
I
PCMCIA/CF pin used as output enable strobe
PCM_IRQ#1, PCM_IRQ#2
O
PCMCIA/CF pins used in memory mode to determine card status for transfers.
Used as an interrupt isgnal in I/O and IDE modes. RDY/IRQ#1 is for device 1.
PCM_RESET
I
PCMCIA/CF reset pin
PCM_REG#
I
PCMCIA/CF pin used to distinguish between common and
register memory in memory mode.
PCM_WAIT#
O
PCMCIA/CF pin to insert wait states in memory and I/O mode. Used as
IORDY in True IDE mode. If there are two sockets in an expansion pack, the expansion
pack must logically OR the WAIT# signals from each socket.
PCM_WE#
O
PCMCIA/CF pin used for write strobing in to CF card in memory
and I/O modes.
PCM_WP
O
PCMCIA/CF pin used as a write protect in memory mode. Used as IOIS16# in
I/O and IDE modes for 16-bit operation. If there are two sockets in an expansion
pack, the expansion pack must logicall OR the WP/IOIS16# signals from each socket.
RDY
O
Ready signal for slow expansion pack devices to insert wait states on the
variable latency I/O port.
DQM[3,1:0]
I
Byte enables for the 32-bit data bus of the static memory and variable latency
I/O port.
MCS[4,2]#
I
Memory bank chip select from processor to use address and data pins for high
bandwidth across expansion pack.
MOE#
I
Memory bank output enable from processor to use address and
data pins for high bandwidth across expansion pack
MWE#
I
Memory bank write enable from processor to use address and
data pins for high bandwidth across expansion pack
Serial Bus Interfaces
Signal Name
Dir.
Description
SPI_SCK
I
clock pin for the SPI interface.
SPI_DI
I
Data input pin for the SPI interface. Pin driven by main unit for data
written to the option pack.
SPI_DO
O
Data output pin for the SPI interface. Pin is driven by expansion pack for
data written to the main unit.
SPI_CS#
I
Chip select pin for the SPI interface.
Miscellaneous Signals
Signal Name
Dir.
Description
ODET1#, ODET2#
O
Expansion pack detect signals. These signals should generate an interrupt when the
expansion pack is inserted or removed.
BATT_FLT
O
Digital, active-high signal that notifies the main unit that the expansion pack battery
is below its critical low level.
INT_OP
O
Expansion pack general purpose interrupt used for various functions such as
FIFO maintenance, polling, etc.
V_ADP
I/O
Positive DC voltage from AC adapter. Power can come from main unit or expansion pack.
V_EBAT
I/O
Positive battery voltage from option pack to main unit.
VS_EBAT
O
Positive terminal sense line for extended battery.
OPT_ON
I
Notifies expansion pack that it can run at full power.
MCHG_EN
I
Notifies expansion pack battery to limit its current.
EBAT_ON
O
Notifies the main unit that the extended battery has sufficient energy to run
the main unit.
CC_ETM
O
Charge signal from expansion pack extended battery to trickle charge the main battery.
CEN_ETM
O
Signal from expansion pack that enables the extended battery to trickle charge the main
battery.
RESET
I
General purpose reset for expansion pack.
PSKTSEL
I
PCMCIA/CF Socket select pin for expansion packs with two sockets.
A_OUTR, AOUTL
I
Line out right and left channels from main unit audio output.
Reserved
TBD
Reserved for future iPAQ H3600 and other programs.
1.12.2. Expansion access cycles
The expansion pack supports three types of access cycles: PCMCIA/CF access
cycles, memory access cycles, and fast I/O access cycles. The signal MRD/WR# is
not a read/write signal, but a buffer direction control signal. Do not use it as
a read/write signal for expansion pack.
1.12.2.1. PCMCIA/CF cycles
PCMCIA/CF cycles are identified by the PCM_CE1#, PCM_CE2#, PCM_OE#, PCM_WE#,
PCM_REG#, PCM_IOR#, PCM_IOW# control signals. The expansion pack interface supports
all standard PCMCIA/CF access cycles, such as memory read/write, I/O read/write,
and configuration register read. SA-1110 CPU supports all PCMCIA/CF 8/16-bit
access cycles with some restrictions. Please see SA-1110 Developer's
Manual Section 10.2.5. and 10.6.
The expansion pack interface supports all two PCMCIA/CF channels. When only one
PCMCIA or CF slot is supported in expansion pack, slot 0 must be decoded first.
1.12.2.2. Memory cycles
Memory cycles are identified by MOE#, MWE#, MCS2#, MCS3, MCAS0#/DQM0#,
MCAS1#/DQM1#. Memory cycles (MCS2#, MCS3#) supports 16-bit bus only.
MCAS0#/DQM0# is the byte enable for D7-0, MCAS1#/DQM1# is the byte enable for
D15-8. The accessible address is in range of A25-A0. The memory access
wait-state is programmable, and MCS2# does not support external ready as fast
I/O cycles. But if MCS3# is programmed as variable latency I/O, it does support
external ready MRDY.
The two memory chip selects support non-burst ROM or flash memory or SRAM,
and burst of four/eight ROM or flash memory(with non-burst write). But only
MCS3# supports variable latency I/O. For details, please see SA-1110 Developer's
Manual "Section 10.2.4. Static memory control Registers(MCS2-0)".
1.12.2.3. Fast I/O cycles
Fast I/O cycles are identified by MOE#, MWE#, MCS4#, MCAS0#/DQM0#,
MCAS1#/DQM1#, MCAS2#/DQM2#, MCAS3#/DQM3#. Fast I/O cycles supports 32-bit bus
only. The accessible addresses are in the range of A10-A0. The fast I/O access
wait-state is programmable, and the wait-state can be extended by external ready
MRDY.
MCAS0#/DQM0# is byte enable for D7-0, MCAS1#/DQM1# is byte enable for D15-8,
MCAS2#/DQM2# is byte enable for D23-16, MCAS3#/DQM3# is byte enable for
D31-24.
The fast I/O cycles support variable latency I/O with external ready and
burst access. For details, please see SA-1110 Developer's
Manual Section 10.2.4. "Static memory control Register(MCS2-0)" and "10.5.5.
Variable Latency I/O interface overview".
The iPAQ H3600 supports two-channel CF/PCMCIA expansion pack decode, but needs
special handling on Card inserted detection(CARD_IND#) and Card IRQ(CARD_IRQ#).
On the expansion pack connector, the PSKTSEL signal can be used to decode which
CF/PCMCIA slot is selected for two-channel CF/PCMCIA expansion packs. PSKTSEL=0
selects channel 0, PSKTSEL=1 selects channel 1.
The default PCMCIA/CF slot is slot 0 and supports external connections. The
second PCMCIA/CF is slot 1 and is for embedded slot only.
1.12.4. Expansion pack Memory space
To support all possible future implementation of expansion packs, we recommend
you program the following the expansion pack memory spaces (virtual addresses).
Memory Space
Chip select
Size
PCMCIA/CF slot 0
PCMCIA/CF slot 0
256 MB
PCMCIA/CF slot 1(embedded)
PCMCIA/CF slot 1
256 MB
Flash ROM or general memory
MCS2#
128 MB
Flash ROM or general memory
MCS3#
128 MB
Fast I/O
MCS4#
2 KB
2. Cradle connector
The iPAQ H3600 uses the cradle connector as a way to connect to the external
world. The cradle connector supports RS-232C, USB and AC adapter power input.
The pin assignment is in following table. The first 12 pins are physical signal
pins, and the rest of the pins are frame ground.
Name
Description
Pin
1
V_ADP
AC adapter power in
2
V_ADP
AC adapter power in
3
DTR
RS-232 Data Terminal Ready
4
GND
Power ground
5
CTS
RS-232 Clear To Send
6
RTS
RS-232 Request To Send
7
TXD
RS-232 Transmit Data (from the SA-1110)
8
RXD
RS-232 Receive Data (from the SA-1110)
9
DCD
RS-232 Data Carry Detect
10
GND
Power ground
11
UDC_P
USB positive data signal
12
USB_N
USB negative data signal
13
FG
Frame ground
14
FG
Frame ground
15
FG
Frame ground
LCD Connector
The LCD connects to the main board via the 90-pin LCD connector.
Name
Description
Pin
Name
Description
Pin
1
TEST4
Test input, connected to 0V
2
TEST5
Test input, connected to 3.3V
3
TEST3
Test input, no connection
4
R31
RED data input
5
R21
RED data input
6
R11
RED data input
7
R01
RED data input
8
G31
GREEN data input
9
G21
GREEN data input
10
G11
GREEN data input
11
G01
GREEN data input
12
B31
BLUE data input
13
B21
BLUE data input
14
B11
BLUE data input
15
B01
BLUE data input
16
XR31
RED data input
17
XR21
RED data input
18
XR11
RED data input
19
XR01
RED data input
20
XG31
GREEN data input
21
XG21
GREEN data input
22
XG11
GREEN data input
23
XG01
GREEN data input
24
XB31
BLUE data input
25
XB21
BLUE data input
26
XB11
BLUE data input
27
XB01
BLUE data input
28
VCOM
Common voltage
29
VVDD
Power supply
30
VVSS1
GND
31
VVSS2
Power supply
32
VST
Pulse input
33
XVST
Pulse input
34
ENB
Pulse input
35
XENB
Pulse input
36
VCK
Pulse input
37
XVCK
Pulse input
38
TEXT1
Test input, no connection
39
TEST2
Test input, no connection
40
RESET
Power-on-reset, connected to R/C
41
HVDD
Power supply
42
HVSS1
GND
43
HVSS2
Power supply
44
HCK1
Pulse input
45
XHCK1
Pulse input
46
HCK2
Pulse input
47
XHCK2
Pulse input
48
HST1
Pulse input
49
XHST1
Pulse input
50
HST2
Pulse input
51
XHST2
Pulse input
52
OE1
Pulse input
53
XOE1
Pulse input
54
OE2
Pulse input
55
XOE2
Pulse input
56
V0
Reference voltage
57
V1
Reference voltage
58
V2
Reference voltage
59
V3
Reference voltage
60
V4
Reference voltage
61
V5
Reference voltage
62
V6
Reference voltage
63
V7
Reference voltage
64
V8
Reference voltage
65
XB02
BLUE data input
66
XB12
BLUE data input
67
XB22
BLUE data input
68
XB32
BLUE data input
69
XG02
GREEN data input
70
XG12
GREEN data input
71
XG22
GREEN data input
72
XG32
GREEN data input
73
XR02
RED data input
74
XR12
RED data input
75
XR22
RED data input
76
XR32
RED data input
77
B02
BLUE data input
78
B12
BLUE data input
79
B22
BLUE data input
80
B32
BLUE data input
81
G02
GREEN data input
82
G12
GREEN data input
83
G22
GREEN data input
84
G32
GREEN data input
85
R02
RED data input
86
R12
RED data input
87
R22
RED data input
88
R32
RED data input
89
TEST6
Test input, connected to 3.3V
90
TEST7
Test input, connected to 3.3V
3. CCFL inverter module
There is a CCFL front light inverter module that provides the high voltage to
light up the CCFL.
The CCFL inverter can be turned off by having the microcontroller set
FL_PWR_ON to low. The communications protocol between the SA-1110 and the
microcontroller is described in TBD.
Support chip - Intel StrongARM SA1111: NOTE this chip is not used in the
core H3600 unit, and cannot be used in expansion packs because it does not support the full SA1110 bus.
