Dell Axim X50/X51(v) Hardware
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x50(v) Mailing List
If you have any information to add to what is on this page already, please do so =] The more we know, the sooner we can make this work.
GPIO PINS
We learn more every day about the GPIOs on the x50. I believe that some of the functions that we haven't yet figured out have to do with our current inability to interface with the ASIC chip, the Toshiba TC200G.
| GPIO# | DIRECTION | AFR | FUNCTION |
| GPIO0 | |||
| GPIO1 | |||
| GPIO2 | |||
| GPIO3 | |||
| GPIO4 | |||
| GPIO5 | |||
| GPIO6 | |||
| GPIO7 | |||
| GPIO8 | |||
| GPIO9 | OUTPUT | HZ_CLK | Real-Time 1hz Clock |
| GPIO10 | OUTPUT | HZ_CLK | Real-Time 1hz Clock |
| GPIO11 | INPUT | n/a | Interupt GPIO 0 is when External Power is connected |
| GPIO12 | INPUT | n/a | Interupt GPIO is 1 when SD card is inserted |
| GPIO13 | |||
| GPIO14 | INPUT | n/a | Interupt GPIO is 0 when USB is connected |
| GPIO15 | OUTPUT | nCS<1> | Static Memory Chip Select Bit 1 |
| GPIO16 | OUTPUT | PWM_OUT<0> | Pulse Width Modulation Channel 0 output (Display Brightness, I think) |
| GPIO17 | OUTPUT | PWM_OUT<1> | Pulse Width Modulation Channel 1 output |
| GPIO18 | INPUT | RDY | Input to detect when external VLIO device is ready to transfer data |
| GPIO19 | |||
| GPIO20 | OUTPUT | nSDCS<2> | SDRAM Chip Select pin 2 |
| GPIO21 | OUTPUT | nSDCS<3> | SDRAM Chip Select pin 3 |
| GPIO22 | OUTPUT | n/a | =1 when bluetooth is enabled, =0 otherwise |
| GPIO23 | OUTPUT | SSPSCLK | Synchronous Serial Port 1 Clock (Master Mode operation) |
| GPIO24 | OUTPUT | SSPSFRM | Synchronous Serial Port 1 Frame (Master Mode operation) |
| GPIO25 | OUTPUT | SSPTXD | Synchronous Serial Port 1 Transmit Data |
| GPIO26 | INPUT | SSPRXD | Synchronous Serial Port 1 Receive Data |
| GPIO27 | |||
| GPIO28 | OUTPUT | I2S_BITCLK | I2S_BITCLK |
| GPIO29 | INPUT | I2S_SDATA_IN | I2S_SDATA_IN |
| GPIO30 | OUTPUT | I2S_SDATA_OUT | I2S_SDATA_OUT |
| GPIO31 | OUTPUT | I2S_SYNC | I2S_SYNC |
| GPIO32 | OUTPUT | MMCLK | MMC/SD Card Bus Clock |
| GPIO33 | OUTPUT | nCS<5> | Static Memory Chip Select Bit 5 |
| GPIO34 | INPUT | FFRXD | Full-Function UART RX |
| GPIO35 | INPUT | FFCTS | Full-Function UART Receive CTS |
| GPIO36 | OUTPUT | n/a | This is set to 1 when charger/cradle power is connected. Aparently, this is controlled by the operating system, and it may be used to signal to other devices that AC power is present. This goes low at the same time that the LCD drops to low power... but that might not mean anything |
| GPIO37 | INPUT | FFDSR | Full-Function UART Receive DSR |
| GPIO38 | |||
| GPIO39 | OUTPUT | FFTXD | Full-Function UART TX |
| GPIO40 | OUTPUT | FFDTR | Full-Function UART TX DTR |
| GPIO41 | OUTPUT | FFRTS | Full-Function UART TX RTS |
| GPIO42 | INPUT | BTRXD | Bluetooth Receive |
| GPIO43 | OUTPUT | BTTXD | Bluetooth Transmit |
| GPIO44 | INPUT | BTCTS | Bluetooth CTS |
| GPIO45 | OUTPUT | BTRTS | Bluetooth RTS |
| GPIO46 | INPUT | STD_RXD | RX Pin for Std UART and Slow IR |
| GPIO47 | INPUT | STD_TXD | TX Pin for Std UART and Slow IR |
| GPIO48 | Output | nPOE | PC Card Output Enable |
| GPIO49 | OUTPUT | nPWE | PC Card Write Enable |
| GPIO50 | Output | nPIOR | PC Card I/O Read |
| GPIO51 | Output | nPIOW | PC Card I/O Write |
| GPIO52 | INPUT | n/a | When 0, Lock is on |
| GPIO53 | |||
| GPIO54 | OUTPUT | nPCE<2> | PC Card Enable 2 (selects PC Card, high byte lane) |
| GPIO55 | OUTPUT | nPREG | PC Card Register Select |
| GPIO56 | INPUT | nPWAIT | PC Card Wait |
| GPIO57 | INPUT | nIOIS16 | PC Card I/O Select 16 (0 or 1, data bus 8 or 16 bits wide) |
| GPIO58 | BIDIRECTIONAL | LDD<0> | LCD Display Module Data Line 0 |
| GPIO59 | BIDIRECTIONAL | LDD<1> | LCD Display Module Data Line 1 |
| GPIO60 | BIDIRECTIONAL | LDD<2> | LCD Display Module Data Line 2 |
| GPIO61 | BIDIRECTIONAL | LDD<3> | LCD Display Module Data Line 3 |
| GPIO62 | BIDIRECTIONAL | LDD<4> | LCD Display Module Data Line 4 |
| GPIO63 | BIDIRECTIONAL | LDD<5> | LCD Display Module Data Line 5 |
| GPIO64 | BIDIRECTIONAL | LDD<6> | LCD Display Module Data Line 6 |
| GPIO65 | BIDIRECTIONAL | LDD<7> | LCD Display Module Data Line 7 |
| GPIO66 | BIDIRECTIONAL | LDD<8> | LCD Display Module Data Line 8 |
| GPIO67 | BIDIRECTIONAL | LDD<9> | LCD Display Module Data Line 9 |
| GPIO68 | BIDIRECTIONAL | LDD<10> | LCD Display Module Data Line 10 |
| GPIO69 | BIDIRECTIONAL | LDD<11> | LCD Display Module Data Line 11 |
| GPIO70 | BIDIRECTIONAL | LDD<12> | LCD Display Module Data Line 12 |
| GPIO71 | BIDIRECTIONAL | LDD<13> | LCD Display Module Data Line 13 |
| GPIO72 | BIDIRECTIONAL | LDD<14> | LCD Display Module Data Line 14 |
| GPIO73 | BIDIRECTIONAL | LDD<15> | LCD Display Module Data Line 15 |
| GPIO74 | OUTPUT | L_PCLK_WD | LCD Display Module Pixel Clock |
| GPIO75 | OUTPUT | L_PCLK_A0 | LCD Display Module Line Clock |
| GPIO76 | OUTPUT | L_PCLK_WR | LCD Display Module Frame Clock |
| GPIO77 | OUTPUT | L_BIAS | LCD Display Module AC Bias |
| GPIO78 | OUTPUT | nCS<2> | Static Memory Chip Select Bit 2 |
| GPIO79 | OUTPUT | nCS<3> | Static Memory Chip Select Bit 3 |
| GPIO80 | OUTPUT | nCS<4> | Static Memory Chip Select Bit 4 |
| GPIO81 | |||
| GPIO82 | |||
| GPIO83 | INPUT | n/a | Headphone audio switch (triggers when audio actually switches to headphones) |
| GPIO84 | INPUT | n/a | = 1 when CF Card is on |
| GPIO85 | |||
| GPIO86 | INPUT | n/a | RE and FE interupt in wince, this = 0 when axim is in the cradle |
| GPIO87 | OUTPUT | n/a | RE and FE interupt in wince, this = 0 when axim is in the cradle |
| GPIO88 | |||
| GPIO89 | |||
| GPIO90 | INPUT | KP_MKIN<5> | Keypad Matrix Key Input, Bit 5 |
| GPIO91 | INPUT | KP_MKIN<6> | Keypad Matrix Key Input, Bit 6 |
| GPIO92 | OUTPUT | MMDAT<0> | MMC/SD Data 0 |
| GPIO93 | |||
| GPIO94 | INPUT | n/a | Input GPIO Falling Edge interupt, 0 when stylus is down |
| GPIO95 | |||
| GPIO96 | INPUT | n/a | Headphone jack detect (triggers when headphone connector is halfway in. Triggers before 83, releases after. |
| GPIO97 | INPUT | KP_MKIN<3> | Keypad Matrix Key Input, Bit 3 |
| GPIO98 | INPUT | KP_MKIN<4> | Keypad Matrix Key Input, Bit 4 |
| GPIO99 | |||
| GPIO100 | INPUT | KP_MKIN<0> | Keypad Matrix Key Input, Bit 0 |
| GPIO101 | INPUT | KP_MKIN<1> | Keypad Matrix Key Input, Bit 1 |
| GPIO102 | OUTPUT | nPCE<1> | PC Card Enable 1 (selects PC Card, low byte lane) |
| GPIO103 | OUTPUT | KP_MKOUT<0> | Keypad Matrix Key Output 0 |
| GPIO104 | OUTPUT | PSKTSEL | PC Card Socket Select |
| GPIO105 | OUTPUT | KP_MKOUT<2> | Keypad Matrix Key Output 1 |
| GPIO106 | |||
| GPIO107 | |||
| GPIO108 | |||
| GPIO109 | BIDIRECTIONAL | MMDAT<1> | MMC/SD Data 1 |
| GPIO110 | BIDIRECTIONAL | MMDAT<2>/MMCS<0> | MMC/SD Data 2 |
| GPIO111 | BIDIRECTIONAL | MMDAT<3>/MMCS<1> | MMC/SD Data 3 |
| GPIO112 | BIDIRECTIONAL | MMCMD | MMC/SD Command |
| GPIO113 | OUTPUT | I2S_SYSCLK | I2S System Clock -- I2S_BITCLK * 4, used by the Codec only |
| GPIO114 | |||
| GPIO115 | |||
| GPIO116 | |||
| GPIO117 | BIDIRECTIONAL | SCL | I2C Serial Clock |
| GPIO118 | BIDIRECTIONAL | SDA | I2C Data/Address Bus |
| GPIO119 | |||
| GPIO120 |
These GPIOs were taken from: http://bateman.dhs.org/~richard/tmp/arm/gpio_map.xml (xml/xslt format)
Please feel free to update the GPIO list if you are aware of any omissions/mistakes.
X50(v) PROCESSOR
PXA270 ARM V4 (see information in the setup panel on your Axim) Enough said. The Axim comes in 3 flavors: the 416Mhz model (A.K.A. x50 Basic) without WiFi, the 520mhz model (x50 Mid) with WiFi, and the 624Mhz model (x50v High) with wifi. I have even been able to over-clock the 624mhz model to 697Mhz (approx.) and upped the system bus to above 200mhz, with the ram sitting at a nice 150mhz with no problems. However, the unit gets a bit hot but I got a huge increase of performance in applications like betaplayerI have also heard reports of people being able to clock up the 312mhz model to 512mhz easily. This must be due to good fabrication techniques so if we could include some dynamic over-clocking/under-clocking based on the CPU load I would be very happy.
http://www.intel.com/design/pca/prodbref/253820.htm
x50(v) RAM BASE ADDRESS
The Base RAM address on the Dell Axim x50(v) is 0xA800_0000. (Unlike most ARM handhelds)RAM CHIPS
X50 (416) RAM chipsInfineon HYB25L256160AC-7.5 SVV05084
Datasheet for these chips can be found
here
FLASH ROM CHIPS
X50 (416) Flash chip number:ROM (right one):
4000L0YBQ0 A4477161 Z4471046A
ROM (left one):
4000L0YBQ0 A4477161 Z4471061A
There is
some board where people are discussing something about flash with that part number (4000L0YBQ0). Unfortunately I can not read this language. If anyone can, than there is chance to find out what is it.
The flash chips in the X50v start with '4400' instead of '4000', and reading the pdf
http://www.intel.com/design/flcomp/datashts/25263302.pdf referenced on JohnCurrey 's page, that may mean they contains a stack of 2 256Mbit chips per package instead of one per package. If the x50 has 64MB flash, and the X50V 128MB flash, then that is likely what is going on (???).
x50v GRAPHICS CONTROLLER
The 2700G graphics chip (INTEL/INTRINSYC 2700G/MARATHON/MBX_Lite 16MB VRAM VERSION) in the x50v is in fact the PowerVR MBX Lite which has been licenced from Imagination Technologies.
So Imagination Technologies developed the PowerVR MBX Lite, they have then licenced the design to Intel/Intrinsyc(2700G), who jointly produced the 2700G from this design. The 2700G is then sold in conjunction with the PXA27x to Dell(x50v) and other OEMs.
http://www.us.design-reuse.com/articles/article10055.html
http://en.wikipedia.org/wiki/PowerVR#PowerVR_MBX
Intel 2700G Product Page
http://www.intel.com/design/pca/prodbref/300571.htm
Other PXA27x/2700G Devices/DVKs
Sophia Systems Sandgate 2G
http://www.sophia.com/Products/SG2G.html
CerfPod 270M
http://www.intrinsyc.com/products/mob_ref_sys/cerfpod_270_m/
Advance Tech M.A.G.I.C.
http://www.advancetc.com/
Intrinsyc's Carbonado
http://www.intrinsyc.com/products/mob_ref_sys/intel_2700g/
http://www.intrinsyc.com/products/mob_ref_sys/
Wiki Info http://en.wikipedia.org/wiki/Intel_2700g
The 2700G can drive an external display up to 1024x768 (with 32-bit color) or 1280x1024 (with 16 bit colour)
The 2700G is based on the
PowerVR MBX chipset. It is the sucessor to the PowerVR2 chip which has been used for the Dreamcast. A Linux driver for that chip
exists <Has anyone contacted the
Linux on Dreamcast Project for help?>
http://www.koders.com/c/fidD8989CA3E7AE523F11E5D97C260230E8B942D62B.aspx
The base of the framebuffer for the Intel 2700g lcd/graphics controller that the x50v uses is located at 0x0C00_0000
These are the values of the 2700g registers when it's running in windows ce:
| DEVICE ID | 0x01727189 | PIXCLKDIV | 0x00000001 |
| SYSCFG | 0x00000000 | LCD_CONFIG | 0x2efa0000 |
| PFBASE | 0x00000000 | ODFBPWR | 0x00000000 |
| PFCEIL | 0x03fdffe0 | PWMCFG | 0x00000003 |
| SYSRST | 0x00000000 | PWM0DIV | 0x00000000 |
| NINTPW | 0x0000001c | PWM0DUTY | 0x00000000 |
| MINTENABLE | 0x0000800f | PWM0PER | 0x00000004 |
| MINTSTAT | 0x00000000 | PWM1DIV | 0x00000000 |
| SINTENABLE | 0x00000000 | PWM1DUTY | 0x00000000 |
| SINTSTAT | 0x00000010 | PWM1PER | 0x00000004 |
| SINTCLR | 0x00000000 | LMCFG | 0x00000027 |
| SYSCLKSRC | 0x00000002 | LMPWR | 0x00000000 |
| PIXCLKSRC | 0x00000001 | LMPWRSTAT | 0x00000000 |
| CLKSLEEP | 0x00000000 | LMCEMR | 0x00000000 |
| COREPLL | 0x00000bb1 | LMTYPE | 0x00000ac8 |
| DISPPLL | 0x00000395 | LMTIM | 0x00073392 |
| PLLSTAT | 0x00000005 | LMREFRESH | 0x00000615 |
| VOVRCLK | 0x00000000 | LMPROTMIN | 0x00000000 |
| PIXCLK | 0x00000001 | LMPROTMAX | 0x03fdfffc |
| MEMCLK | 0x00000001 | LMPROTCFG | 0x00000000 |
| SDCLK | 0x00000001 | LMPROTERR | 0x00000000 |
VIDGAM[0:16]
0ffe2200 | 0x00000000 0x00101010 0x00202020 0x00303030 0ffe2210 | 0x00404040 0x00505050 0x00606060 0x00707070 0ffe2220 | 0x00808080 0x00909090 0x00a0a0a0 0x00b0b0b0 0ffe2230 | 0x00c0c0c0 0x00cfcfcf 0x00e0e0e0 0x00f0f0f0 0ffe2240 | 0x00ffffff
GFXGAM[0:16]
0ffe2250 | 0x00000000 0x00101010 0x00202020 0x00303030 0ffe2260 | 0x00404040 0x00505050 0x00606060 0x00707070 0ffe2270 | 0x00808080 0x00909090 0x00a0a0a0 0x00b0b0b0 0ffe2280 | 0x00c0c0c0 0x00cfcfcf 0x00e0e0e0 0x00f0f0f0 0ffe2290 | 0x00ffffff
Plane Control
| GSCTRL | 0x3c0efa7f |
| GBBASE | 0x00000000 |
| GDRCTRL | 0x00ffffff |
| GSCADR | 0x80000000 |
| GSADR | 0x0ec00000 |
| GPLUT | 0x00000000 |
Video Display
| VSCTRL | 0x0600780f |
| VBBASE | 0x00000000 |
| VCMSK | 0x00ffffff |
| VSCADR | 0x01000000 |
| VUBASE | 0x00000000 |
| VVBASE | 0x00000000 |
| VSADR | 0x00000000 |
x50(v) AUDIO CHIP: WM8750
The x50 and x50v both use the same audio chip, ax50(v) CPLDs
The x50(v) has two Xilinx CPLDs: Xilinx CoolRunner-II 2C64, 64 Macrocells, CP56 0.5mm BGA package, speed rating 7, 0..70 Celcius, 1.8..3.3V,
1..263Mhz, 45 I/O pins in 2 banks
part datasheet
(the "Smaller out one")
Xilinx CoolRunner-II 2C128, 128 Macrocells, CP132 0.5mm BGA package, speed rating 7, 0..70 Celcius, 1.8..3.3V, 1..270Mhz, 100 I/O pins in 2 banks
(the "The chips uper than RAM" close to the RAM chips)
CoolRunner-II family webpage,
family datasheet, and
package details, and
part markings
The 2C128 is accompanied by a Texas Instruments LD245A, a
16-bit bus transceiver with 3-state outputs, likely interfacing the CPLD to some kind of 16-bit bus.
x50(v) GATE ARRAY (ASIC)
Toshiba TC200G series part TC200G04XB-0024, 3.0/3.3v, 0.4 micron, 22k/38k gates equivalent (2/3 layers), max 104...208 pins,
family webpage and
product brief
(the "Biggest out chip")
A Gate Array ASIC is a digital chip similar to a CPLD, but with different performance characteristics, pricing, and generally a much higher amount of logic that they can hold. A Gate Array ASIC can be produced with a lower
NRE than a cell-based or full custom ASIC, in exchange for a higher unit price, higher power usage, and lower speed (other alternatives are the structured ASIC and FPGA).
Wikipedia on Gate Arrays and
ASICs. In summary: the ASIC could be doing any digital logic function that can be done with 22000 or 38000
NAND Logic Gates.
The Asus MyPal730 has a TC200G too. It's unlikely, but not impossible that the two are identical (maybe they each sourced the same chip/design for the same feature).
There is also a 240Mhz
TI THS8135 video DAC close to it on the x50v, most likely used by the Intel 2700g.
x50(v) WIFI
JohnCurrey mentions on his page, that it's a
From the FCC pictures, it appears that in the x50v, the TNETW1100B is flanked by the
MAXIM2820 Wlan tranceiver. I'm not totally sure if I read the label correctly, but it looks like it and the pin count matches, and it's under a combined shield with an area that seems to include a bandpassfilter (the white block) just like in the picture at the bottom of the
maxim appnote.
See DellAximX51vWifiInvestigationNotes.
X50 Bluetooth
It seems to be a BRF6150. SeeConnector
X50v Pin-Out (from: http://www.aximsite.com/boards/showthread.php?t=59614&page=2&pp=25) Bottom Connector back of x50v ______----________________________----______ | 1 17 19 35| | _-_-_-_-_-_-_-_-_- _-_-_-_-_-_-_-_-_- | | 2 18 20 36 | -------------------_____-------------------- front of x50v X50V uses TTL serial interface (3.3 v). DTR 14 DSR 13 TX 11 RX 10 RTS 9 CTS 8 VGA Pin# / x50v Pin# / Label Function 1 33 RED Red color signal 2 35 GREEN Green color signal 3 31 BLUE Blue color signal 4 - ID2 Monitor identification bit 2 5 - N.C. Not Connected 6 34 GND-RED Ground Red signal 7 36 GND-GREEN Ground Green signal 8 32 GND-BLUE Ground Blue signal 9 - N.C. Not Connected 10 30 GND-SYNC Ground Sync signal 11 - ID1 Monitor identification bit 1 12 26 ID0 Monitor identification bit 0 13 28 H-SYNC Horizontal Synchronization 14 29 V-SYNC Vertical Synchronization 15 - N.C. Not connected *********** '''Note: you need a MAX 232 for serial level conversion or you will damage your PDA!''' ************
Expressed in a possibly more useful format,
| Axim Pin | Use |
| 1 | +5.4V Input from external power supply |
| 2 | +5.4V Input from external power supply |
| 3 | +5.4V Input from external power supply |
| 4 | +5.4V Input from external power supply |
| 5 | 1.68V Output, possibly for cradle or access detection |
| 6 | 1.68V Output, possibly for cradle or access detection |
| 7 | unknown |
| 8 | Serial CTS |
| 9 | Serial RTS |
| 10 | Serial RX |
| 11 | Serial TX |
| 12 | Ground |
| 13 | Serial DSR |
| 14 | Serial DTR |
| 15 | Ground |
| 16 | Ground |
| 17 | Ground |
| 18 | unknown |
| 19 | unknown |
| 20 | unknown (Known not to be ground) |
| 21 | USB client +5 VDC |
| 22 | USB client DATA+ |
| 23 | USB client DATA- |
| 24 | unknown (Known not to be ground) |
| 25 | 5V TTL output ? |
| 26 | VGA ID0 monitor identification bit 0 (VGA Pin 12) |
| 27 | 5V TTL output ? |
| 28 | VGA HSYNC (VGA Pin 13) |
| 29 | VGA VSYNC (VGA Pin 14) |
| 30 | VGA SYNC ground (VGA Pin 10) |
| 31 | VGA BLUE signal (VGA Pin 3) |
| 32 | VGA BLUE ground (VGA Pin 8) |
| 33 | VGA RED signal (VGA Pin 1) |
| 34 | VGA RED ground (VGA Pin 6) |
| 35 | VGA GREEN signal (VGA Pin 2) |
| 36 | VGA GREEN ground (VGA Pin 7) |
TOUCHSCREEN
X50(v)
All three models use the Texas Instruments ADS 7846N chip, which interfaces with the pxa cpu on it's first SSP (synchronous serial port).
Some information can be found here:
http://focus.ti.com/docs/prod/folders/print/ads7846.html
X51(v)
X51v at least uses the Texas Instruments TSC 2046 chip, also interfaced with the pxa cpu on it's first SSP.
Some information can be found at:
http://focus.ti.com/docs/prod/folders/print/tsc2046.html
Keys
The Axim family uses the pxa27x matrix keyboard controller, with 7 rows and 3 columns. Keys are mapped as below (at least on X51v).| Key | Row | Column |
| KEY_WLAN | 0 | 0 |
| KEY_UP | 0 | 2 |
| KEY_RECORD | 1 | 0 |
| KEY_DOWN | 1 | 2 |
| KEY_CALENDAR | 3 | 0 |
| KEY_RIGHT | 3 | 2 |
| KEY_CONTACTS | 4 | 0 |
| KEY_LEFT | 4 | 2 |
| KEY_EMAIL | 5 | 0 |
| KEY_SELECT | 5 | 2 |
| KEY_HOME | 6 | 0 |
The power key is not managed by the matrix keyboard controller.